Select circuits or multiplexer (MUX) circuits are a well known type of circuit design. They are widely utilized in various circuit designs of ICs and systems. Multiplexer circuits also have wide applications in programmable logic devices (PLDs); one circuit that utilizes MUX circuits in a PLD is a lookup table (LUT). A PLD is a well-known type of IC that can be programmed to perform specified logic functions. One type of PLD is a field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated block random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic is typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
One programmable element commonly found in FPGA logic blocks is the LUT. In one example, a six input LUT may be viewed as a 64:1 MUX circuit or as a single 64-bit RAM that is addressable by a number of input signals (e.g., six input signals). For instance, a 64:1 LUT circuit may have 64 bit memory array coupled to its input and six inputs selecting/addressing a bit from the memory array. Programming predetermined values into the memory array and using the input signals, the LUT can implement any function based on the input values. Performance parameters, such as speed and/or power, and versatility, such as larger logic functions, are in the forefront of LUT implementations.
Therefore, it is desirable to provide a multiplexer circuit that is versatile and have high performance, such as reduced propagation delay.